Course: ECE 422/L. Computer Organization and Design and Lab (3/1)
Prerequisite: ECE 220. Corequisite: ECE 422L. This course introduces the fundamentals of computer organization, emphasizing instruction set architecture (ISA) based on the Reduced Instruction Set Computer (RISC) model. Topics include computer performance analysis, the design of datapaths and control paths in RISC-based CPUs, and the development of single-cycle, multicycle, and pipelined processors. Students will also learn how to design key hardware modules such as arithmetic-logic units, pipelined datapath and control units, hazard detection and correction units, input-output units, and buses. The course explores memory hierarchy and organization, including cache and virtual memory systems. The laboratory complements the lecture by providing hands on experience in assembly programming of microprocessors and RISC based instruction set architecture. Students will learn how to write, compile, and debug RISC based assembly programs using RISC based simulators. Available for graduate credit. 3 hours lecture, one 3-hour lab per week.