Prerequisite: ECE 420. Recommended Corequisite: ECE 524. The lab accompanying course ECE 524 covers modeling of digital systems and electronic circuit design hierarchy and the role of methodology in FPGA/ASIC design. Hardware Description Language, VHDL, simulation and synthesis tools are utilized to elaborate the material covered throughout the course. The lab introduces the systematic top-down design methodology to design complex digital hardware such as FPGAs and ASICs. FPGA and ASIC design flow as well as design optimization techniques are discussed. For FPGAs, Xilinx Virtex and Actel SX architecture are covered. Individual and group projects are assigned to students. 3 hours lab per week.

Fall-2020 - Schedule of Classes

ECE 524L

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