- Schedule of Classes
Prerequisite: ECE 320. Corequisite: ECE 422. The lab introduces a systematic approach to the design of modern RISC based pipelined processors. The laboratory complements the lecture course ECE 422 by providing hands on experience in assembly programming of microprocessors and RISC based instruction set architecture (ISA). Other topics to be included are evaluation of computer performance evaluation, design of arithmetic/logic units, data path and control unit synthesis, single cycle CPUs, multicycle CPUs, and pipelined processors, hierarchical memory systems.