ECE 524/L. FPGA/ASIC Design and Optimization Using VHDL and Lab (3/1)

Prerequisite: ECE 420. Corequisite: ECE 524L. This course covers top down design methodology for FPGA and ASIC using VHDL. Hardware Description Language, (VHDL) modeling, simulation and synthesis tools are utilized to elaborate the material covered throughout the course. Xilinx (the Virtex series) and Actel (the SX and AX series) FPGA architectures and design methodologies are studied. Several sample designs are targeted and tested for each FPGA technology. ASIC design flow and design optimization techniques are discussed. ASIC design flow, constraint file generation and test benches also are studied, along with their applications to some designs samples. The use of FPGAs in space and military applications and their reliability issues are discussed. Lab: The lab covers modeling of digital systems and electronic circuit design hierarchy and the role of methodology in FPGA/ASIC design. Hardware Description Language, VHDL, simulation and synthesis tools are utilized to elaborate the material covered throughout the course. The lab introduces the systematic top-down design methodology to design complex digital hardware such as FPGAs and ASICs. FPGA and ASIC design flow as well as design optimization techniques are discussed. For FPGAs, Xilinx Virtex and Actel SX architecture are covered. Individual and group projects are assigned to students. 3 hours lecture, 3 hours lab per week.