ECE 524/L. FPGA/ASIC Design and Optimization Using HDL and Lab (3/1)

Prerequisite: ECE 420 or ECE 427. Corequisite: ECE 524L. This course introduces a top-down design methodology for FPGA and ASIC development using Hardware Description Language (HDL), and trains students for RTL design and front-end design of digital circuits. Students will engage with HDL, modeling, simulation, and synthesis tools to reinforce the theoretical concepts discussed in class. The course explores FPGA architectures from Xilinx, focusing on design techniques, optimization, performance analysis and improvement, and timing analysis of digital circuits. Several sample designs will be implemented and tested on different FPGA platforms. In addition, the course covers the ASIC design flow and various design optimization techniques, including constraint file generation and testbench creation, with practical applications to selected sample designs. Lab: The lab component focuses on the modeling of digital systems and the role of hierarchical design methodologies in FPGA and ASIC development. HDL, simulation, and synthesis tools will be applied to reinforce lecture content, guiding students through a systematic, top-down approach for designing complex digital hardware. The lab covers FPGA and ASIC design flows, as well as optimization techniques. Students will work with Xilinx design software and FPGA development kits to learn how to design, test, debug, modify, and configure FPGAs. Both individual and group projects are assigned. 3 hours of lecture and 3 hours of lab per week.